This was followed by securing the chips to a sample holder using an electrically conductive adhesive to improve penetration of the high energy electrons from the SEM electron gun. He decided to use Intel's Core i9-10900K processor and compare it to AMD's Ryzen 9 3950X under a scanning electron microscope (SEM).įirst, der8auer took both chips and detached them from their packages then he proceeded to grind them as much as possible so SEM could do its job of imaging the chips sans the substrate and protective barrier. German hardware overclocker and hacker, der8auer, has decided to see how one production level silicon compares to another, and he put it to the test. Compare that to AMD's best, a Ryzen 3000 series processor based on Zen 2 architecture, which is built on TSMC's 7 nm node, and you would think AMD is in clear advantage there. However, IBM currently has working partnerships with both Samsung and Intel, who might integrate this process into their own future production.Currently, Intel's best silicon manufacturing process available to desktop users is their 14 nm node, specifically the 14 nm+++ variant, which features several enhancements so it can achieve a higher frequencies and allow for faster gate switching. We don't yet have any announcements of real products in development on the new process. Comparing the new design to TSMC 7 nm is well and good, but TSMC's 5 nm process is already in production, and its 3 nm process, which has a very similar transistor density, is on track for production status next year. Comparing transistor densities to existing processes also seems to take some of the wind from IBM's sails. (TSMC builds processors for AMD, Apple, and other high-profile customers.)Īlthough IBM claims that the new process could "quadruple cell phone battery life, only requiring users to charge their devices every four days," it's still far too early to ascribe concrete power and performance characteristics to chips designed on the new process. ManufacturerĪs you can see in the chart above, the simple "nanometer" metric varies pretty strenuously from one foundry to the next-in particular, Intel's processes sport a much higher transistor density than implied by the "process size" metric, with its 10 nm Willow Cove CPUs being roughly on par with 7 nm parts coming from TSMC's foundries. Cutress got IBM to translate "the size of a fingernail"-enough area to pack 50 billion transistors using the new process into 150 square millimeters. To get a better idea of how IBM's new 2 nm process stacks up, we can take a look at transistor densities, with production process information sourced from Wikichip and information on IBM's process courtesy of Anandtech's Dr. Foundries still refer to a process size in nanometers, but it's a "2D equivalent metric" only loosely coupled to reality, and its true meaning varies from one fabricator to the next. Originally, process size referred to the literal two-dimensional size of a transistor on the wafer itself-but modern 3D chip fabrication processes have made a hash of that. What's less clear is exactly what that means in the first place. If you've followed recent processor news, you're likely aware that Intel's current desktop processors are still laboring along at 14 nm, while the company struggles to complete a migration downward to 10 nm-and that its rivals are on much smaller processes, with the smallest production chips being Apple's new M1 processors at 5 nm. IBM says its new process can produce CPUs capable of either 45 percent higher performance or 75 percent lower energy use than modern 7 nm designs. On Thursday, IBM announced a breakthrough in integrated circuit design: the world's first 2 nanometer process.
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